| K | Memory | |
| 8 | NOR Flash | |
| X | Small Classification | 5 = Dual bank die stack6 = Single bank die stack7 = Multiplexed DDP8 = De-Multiplexed DDPA = De-Multiplexed burstB = Single bank boot blockC = MLC De-MuxedD = Dual bank boot blockF = MLC muxedG = MLC de-multiplexed DDPH = MLC multiplexed DDPL = Intel NOR flashP = Page modeS = Multiplexed burstT = Mitsubishi NOR flashU = Single bank uniform block |
| XX | Density | - Dual bank die stack64 = 64M (3232,824)65 = 64M (3232,1616)- Single bank die stack27 = 128M(2CS)64 = 64M(32M,32M)55 = 256Mbit(16Mx16)- Multiplexed DDP11 = 512M(1CS, 32Bank)13 = 512M(2CS)56 = 256M(16Bank)1G = 1G(16Bank)- De-Multiplexed DDP12 = 512M(16Bank)13 = 512M(2CS)56 = 256M(16Bank)1G = 1G(16Bank)- De-Multiplexed Burst12 = 512M(16Bank)28 = 128M(8M,16Bank)32 = 32M(2M, 16Bank)56 = 256M(16Bank)64 = 64M(4M, 16Bank)- Single Bank Boot Block16 = 16M27 = 128M(2CS)28 = 128M32 = 32M64 = 64M80 = 8M- MLC De-Muxed12 = 512M(16Bank)56 = 256M(16Bank)1G = 1G(16Bank)- Dual Bank Boot Block(Bank1, Bank2)15 = 16M(2M, 14M)16 = 16M(4M, 12M)17 = 16M(8M, 8M)32 = 32M(8M, 24M)33 = 32M(16M, 16M)62 = 64M(8M, 24M)63 = 64M(16M, 48M)64 = 64M(24M, 40M)65 = 64M(32M, 32M)- MLC Muxed12 = 512M(16Bank)56 = 256M(16Bank)1G = 1G(16Bank)MLC De-Multiplexed DDP11 = 512M(1CS, 32Bank)13 = 512M(2CS)- MLC Multiplexed DDP11 = 512M(1CS, 32Bank)13 = 512M(2CS)- Intel NOR Flash56 = 256M(8Bank)28 = 128M(16Bank)- Page Mode28 = 128M(8M, 16Bank)56 = 256M(16Bank)64 = 64M(4M, 16Bank)- Multiplexed Burst12 = 512M(16Bank)28 = 128M(8M, 16Bank)32 = 32M(16Bank)56 = 256M(16Bank)64 = 64M(4M, 16Bank)- Mitsubishi NOR Flash64 = 64M(4,4,28,28)- Single Bank Uniform Block16 = 16M27 = 128M(2CS)28 = 128M32 = 32M64 = 64M80 = 8M |
| XX | Organization | 08 = x815 = x1616 = x8/x1632 = x16/x32 |
| X | Power Supply | 8 = 1.8V (1.7V to 1.9V)E = 1.8V (1.7V to 1.95V)F = 1.8V / Vio=3.0V (2.2V to 3.3V)K = 2.8V (2.5V to 3.1V)L = 1.8V (1.65V to 1.95V)R = 2.0V (1.8V to 2.2V)S = 2.5V (2.3V to 2.7V)U = 3.0V / 3.3V (2.7V to 3.6V)Y = 3.0V (2.7V to 3.3V)V = 3.0V (2.7V to 3.1V) |
| X | Device Type | 1 = 4MSRAM MCP2 = 8M SRAM MCP3 = 16M SRAM MCP4 = 128M SDR H-die MCP5 = 16M UtRAM MCP6 = 32M UtRAM MCP7 = 128M DDR MCP8 = OneNAND, SDRAM MCP9 = 128M MDDA = 8M Boot block MCP(Top)B = Bottom boot blockC = BootBlock(chip1-bottom, chip2-top)D = 16M Boot block MCP(Top)E = 16M Boot block MCP(Bottom)F = 16M Dual bank MCP(Top)G = 16M Dual bank MCP(Bottom)H = 32M Dual bank MCP(Top)I = 32M Dual bank MCP(Bottom)J = 64M Dual bank MCP(Top)K = 64M Dual bank MCP(Bottom)L = 4M Boot block MCP(Top)M = Top boot block in DDPN = Bottom boot block in DDPP = 256M DDR MCPQ = Top and bottom boot blockS = Uniq IDT = Top boot blockZ = Uniform block |
| X | Generation | M = 1st generationA = 2nd generationB = 3rd generationC = 4th generationD = 5th generationE = 6th generationF = 7th generationL = Intel 1st generationT = Mitsubishi 1st generation |
| X | Package Type | 1 = MCPC = Chip BIZW = WaferD = FBGA(LF)E = FBGA (LF, 1mm pitch)F = FBGAL = TBGA(LF)T = TBGAP = TSOP1(LF)S = FBGA(LF, OSP)U = FBGA(OSP)Y = TSOP1 |
| X | Temperature Range | 0NoneC = CommercialE = ExtendedI = Industrial |
| XX | Speed | 03 = 85ns07 = 70ns08 = 80ns09 = 90ns12 = 120ns1A = 100ns(C/F 40MHz)1B = 100ns(C/F 54MHz)1C = 100ns(C/F 66MHz)1D = 100ns(C/F 83MHz)1E = 100ns(C/F 108MHz)1F = 100ns(C/F 133MHz)2A = 70ns/20ns(Page)2B = 80ns/25ns(Page)2C = 90ns/30ns(Page)2D = 85ns/25ns(Page)4A = 55ns/20ns(Page)4B = 60ns/25ns(Page)4C = 65ns/25ns(Page)4D = 70ns/30ns(Page)6F = 66ns(C/F 133MHz)7A = 70ns(C/F 75MHz)7B = 88.5ns(C/F 54MHz)7C = 70ns(C/F 66MHz)7D = 70ns(C/F 80MHz)7E = 70ns(C/F 40MHz)9A = 90ns(C/F 40MHz)9B = 95ns(C/F 66MHz)9C = 90ns(C/F 54MHz)9D = 90ns(C/F 80MHz)DS = Daisychain sample00 = None(containing exception handling code) |
